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ATmega128
Pull-up and Bus-
keeper
Timing
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in “External Memory Control Register B – XMCRB”
on page 32 . W hen enabled, the bus-keeper will ensure a defined logic level (zero or one) on the
AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.
External Memory devices have different timing requirements. To meet these requirements, the
ATmega128 XMEM interface provides four different wait-states as shown in Table 4 . It is impor-
tant to consider the timing specification of the External Memory device before selecting the wait-
state. The most important parameters are the access time for the external memory compared to
the set-up requirement of the ATmega128. The access time for the External Memory is defined
to be the time from receiving the chip select/address until the data of this address actually is
driven on the bus. The access time cannot exceed the time from the ALE pulse must be
asserted low until data is stable during a read sequence (See t LLRL + t RLRH - t DVRH in Tables 137
through Tables 144 on pages 328 - 330). The different wait-states are set up in software. As an
additional feature, it is possible to divide the external memory space in two sectors with individ-
ual wait-state settings. This makes it possible to connect two different memory devices with
different timing requirements to the same XMEM interface. For XMEM interface timing details,
please refer to Table 137 to Table 144 and Figure 157 to Figure 160 in the “External Data Mem-
ory Timing” on page 328 .
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
Figure 13. External Data Memory Cycles without W ait-state (SR W n1=0 and SR W n0=0)
T1
T2
T3
T4
System Clock (CLK CPU )
ALE
A15:8
Prev. addr.
Address
DA7:0
Prev. data
Address
XX
Data
W R
DA7:0 (XMBK = 0)
Prev. data
Address
Data
DA7:0 (XMBK = 1)
Prev. data
Address
XXXXX
Data
XXXXXXXX
RD
Note:
1. SR W n1 = SR W 11 (upper sector) or SR W 01 (lower sector), SR W n0 = SR W 10 (upper sector) or
SR W 00 (lower sector). The ALE pulse in period T4 is only present if the next instruction
accesses the RAM (internal or external).
28
2467X–AVR–06/11
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